1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to a network control apparatus and a network control method. More particularly, the present invention relates to a network control apparatus and a network control method which control an address and data transmission/reception between a master intellectual property and a slave intellectual property
2. Description of Related Art
As minimization of a semiconductor chip is realized due to development of semiconductor manufacturing technologies and circuit designing, a plurality of functional modules embedded in separate chips are currently integrated into a single chip.
A system-on-chip (SoC) is a semiconductor technology which integrates all components or other electronic systems into a single chip, and development of the SoC enables convergence of a computer, communication, broadcasting, and the like.
Also, due to the development of the SoC, an application specific integrated circuit (ASIC) and an application specific standard product (ASSP), which conventionally have been embedded in separate chips, are integrated into a single chip.
Specifically, a module in the SoC, which performs a function of a conventional ASIC or ASSP, is referred to as an intellectual property (IP). A study for connecting a plurality of IPs, which are distributively embedded in a chip, is briskly conducted with regard to a process of substituting an IP in the SoC for a function embedded in separate chips.
A connection method based on a Bus is a mainly used to connect the IPs. However, the connection method based on the Bus has a problem in that other IPs are not able to use a Bus when even a single IP uses the Bus. Accordingly, as a number of IPs embedded in the chip is increased, and an amount of information flowing between the IPs is increased, the SoC using the Bus architecture is reaching its practical limitation.
To solve the functional limitation of the SoC using the Bus architecture, a network-on-chip (NoC) technology has been recently proposed. The NoC connects the IPs by suitably adapting a general network technology to the SoC.
Alternatively, an advanced microcontroller Bus architecture (AMBA) by ARM Holdings PLC has been proposed, the AMBA conventionally being used as a Bus standard for connection and management between IPs embodied in the SoC. There are a high-performance Bus (AHB), an advanced peripheral Bus, and an advance extensible interface (AXI) as examples of derivative Bus architectures included in the AMBA. The AXI is an interface protocol of an IP, and includes developed functions such as a multiple outstanding address function and a data interleaving function.
The AXI Bus method includes a developed function, however quite a number of lines are required to embody an address path and a data path since the address path and the data path are physically separate.
Accordingly, the AXI Bus has problems in that, the AXI Bus requires a large amount of space, connection between IPs is difficult, and power consumption is great when voltage switching occurs in lines that configure the address path and the data path.
Therefore, a new network control apparatus and method, which can connect IPs, which are suitably designed for the AXI Bus in a chip embodied using the SoC, have an effective Bus architecture, and utilize advantages of the AXI, is required.